1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly to a semiconductor device structure which is suitable for an integrated circuit of high performance.
2. Background of the Related Art
Currently, in order to realize high performance and high integration of a semiconductor integrated circuit, technologies for enabling high speed operation of a device and for minimizing a chip size have been suggested.
For example, methods for reducing an area occupied by source and drain impurity regions or a length of a channel are under study. According to one method, when two identical elements, such as NMOS transistors of a NAND circuit, or PMOS transistors of a NOR circuit, are serially connected, the two elements use one impurity region in common, thereby reducing an entire impurity region.
FIG. 1A is general NAND circuit diagram, wherein xe2x80x98Axe2x80x99 shows a structure in which two NMOS transistors are serially connected. FIG. 1B is a general NOR circuit diagram, wherein xe2x80x98Bxe2x80x99 shows a structure in which two PMOS transistors are serially connected.
FIG. 1C shows a structure of a path transistor in which NMOS transistors are serially connected. It should be understood that PMOS transistors could be similarly connected.
A structure of a related art semiconductor device will be described with reference to the accompanying drawings.
FIG. 2 is a sectional view of a related art semiconductor device and shows xe2x80x98Axe2x80x99 of FIG. 1A.
Referring to FIG. 2, the related art semiconductor device includes a semiconductor substrate 21, first and second gate electrodes 23 and 24 formed on the semiconductor substrate 21 at a regular interval, insulating sidewalls 25 formed at both sides of each of the first and second gate electrodes 23 and 24, a common impurity region 26 having an LDD (lightly doped drain) structure formed in the substrate between the first gate electrode 23 and second gate electrode 24, and first and second impurity regions 27 and 28 each having an LDD structure formed at one side of each of the gate electrodes 23 and 24 to oppose the common impurity region 26.
The gate electrodes 23 and 24 have a gate insulating layer 29 formed between each of the gate electrodes 23 and 24 and the semiconductor substrate 21.
The first impurity region 27 is used as a source (or drain) region, the second impurity region 28 is used as a drain (or source) region, and the common impurity region 26 is used as drain/source regions.
In the aforementioned semiconductor device, if a high voltage signal is applied to the first and second gate electrodes 23 and 24, a signal charge is transmitted from the first impurity region 27 to the common impurity region 26, and then to the second impurity region 28.
When the semiconductor device shown in FIG. 2 corresponds to xe2x80x98Bxe2x80x99 of the NOR circuit shown in FIG. 1B, if a low voltage signal is applied to the first and second gate electrodes 23 and 24, a signal charge is transmitted from the first impurity region 27 to the common impurity region 26, an then to the second impurity region 28.
However, the related art semiconductor device has the following problems.
The size of the semiconductor device is increased by the common impurity region existing between the two gate electrodes, and a voltage drop is caused by resistance of source, drain and LDD regions, thereby reducing a driving current and lowering the operating speed.
Accordingly, an object of the present invention is to solve at least the problems and disadvantages of the related art.
Another object of the present invention is to provide a semiconductor device in which an impurity region between two gates is eliminated to minimize a size of the device and to shorten a length of a channel, thereby improving an operating speed of the device.
Additional advantages, objects, and features of the invention will be set forth in part in the description which follows and in part will become apparent to those having ordinary skill in the art upon examination of the following or may be learned from practice of the invention. The objects and advantages of the invention may be realized and attained as particularly pointed out in the appended claims.
To achieve the objects and in accordance with the purposes of the invention, as embodied and broadly described herein, a semiconductor device having two or more PMOS or NMOS transistors serially connected to each other includes a first impurity region and a second impurity region formed in a surface of a semiconductor substrate at a regular interval; a gate insulating layer formed on the semiconductor substrate between the first impurity region and the second impurity region; and two or more gate electrodes formed on the gate insulating layer to be insulated from each other.